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an10960 dali slave using the lpc1112 rev. 1 ? 22 july 2010 application note document information info content keywords lpc1112, cortex m0, uba2014, dali slave unit, hftl ballast abstract this application note describes t he design of a dali (digitally addressable lighting interface) slave unit, based on the lpc1112 microcontroller from nxp semiconductors.
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 2 of 12 contact information for additional information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com revision history rev date description 01 20100722 initial revision
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 3 of 12 1. introduction this report describes the design of a dali (digitally addressable lighting interface) slave unit, based on the lpc1112 from nxp se miconductors. it illu strates how to add dali functionality to an existing hf-tl dimmable ballast design. in that case, the complete (dali ballast) application (see fig 1 ) contains two main parts: 1. the ballast control section, based on a uba2014 (not discussed in this app. note) 2. the dali slave control section, based on an lpc1112 the communication between the ballast and the external world is done with just two signals (tx and rx), allowing the ballast to communicate bi-directional with the dali system network. an optical isolated digita l interface assures high voltage isolation between the dali inputs and the lamp output stage. fig 1. dali ballast simplified block diagram 1.1 dali protocol the international standard (iec 60929) dali-b us communication protocol is intended for use in digital tl-ballast intelligent lighting sy stems. in a typical a pplication, a dali-bus consists of one controller (master), and multiple slave units (normally tl-ballasts). it can control up to 64 different slaves (ballasts) wi thin the same control system. it?s possible to transmit commands to single ballasts or to a group of ballasts. for electrical bus specification please refe r to the international standard. for dali command protocol, addressing modes and specific protocol timing requirements, see nxp application note an10760 (see references ). uba2014 f half bridge lc(r) half bridge lc(r) mains rectifier mains rectifier 230vac emi + pfc u -lamp i -lamp lpc1112 pwm optical isolation cap gpo dali hf-tl ballast
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 4 of 12 1.2 dali ballast ballasts are able to have 1 short address, 16 group addres ses and will also react to broadcast commands. additionally, they are able to store 16 scenes, a fade rate, a fade time, and min-, max-, power-on and system failure levels. al these parameters (constant s) are stored in persistent (flash) memory and can be changed by the master. table 1 gives a complete overview of the dali ballast constants, variables and their default or ?factory? programmed values. table 1. dali ballast d eclaration of variables variable default value reset value range memory type actual dim level not applicable 254 0, min ? max 1 byte ram power on level 254 no change 1 ? 254 1 byte flash (iap) system failure level 254 no change 0 ? 255 (mask) 1 byte flash (iap) min level physical min level no change ph ys min ? max level 1 byte flash (iap) max level 254 no change min level ? 254 1 byte flash (iap) fade rate 7 (45 steps/sec) no change 1 ? 15 1 byte flash (iap) fade time 0 (no fade) no change 0 ? 15 1 byte flash (iap) short address 255 (no address) no change 0 ? 63, 255 (mask) 1 byte flash (iap) search address 0xffffff 0xffffff 0 ? 0xffffff 3 bytes ram random address 0xffffff no change 0 ? 0xffffff 3 bytes flash (iap) group 0 - 7 00000000 (no group) no change 0 ? 255 1 byte flash (iap) group 8 - 15 00000000 (no group) no change 0 ? 255 1 byte flash (iap) scene 0 - 15 16 x 255 (mask) no change 16 x 0 ? 255 (mask) 16 bytes flash (iap) status info not applicable 0?100??? 0 ? 255 1 byte ram version number factory burn-in factory burn-in 0 ? 255 1byte flash physical min level factory burn-in factory burn-in 1 ? 254 1 byte flash 1.3 frame structure the ballast operates in a master-slave m ode where the ballast is the slave and any control unit is the master. a command sent by the master is called a ?forward frame? and consists of bi-phase coded bits: 1 start bit (logical ?1?), 1 address byte, 1 data byte and 2 stop bits (idle). an answer from the ballast (slave), called a ?backward frame? shall consist of bi-phase coded bits: 1 start bit (logical ?1?), 1 data byte and 2 stop bits (idle). the frame structure is tested in the receiving unit. in case of code violation the frame is ignored. 1.7 ms after the occurrence of a code violation the ballast must be ready again for data reception. query commands from the master are of the kind that they can be answered with ?yes?, ?no? or 8-bit inform ation. the answers (b ackward frames) are: ? 'yes': 1111 1111 ? 'no': the ballast does not react (sends nothing)? ? 8-bit information: xxxx xxxx
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 5 of 12 1.4 addressing dali ballasts when leaving the factory ballasts have no short and no group address assigned (see table 1 ). so, after a dali system installation, t he master first needs to allocate a short address to each individual slave. there are two ways to do this: random addressing 1. the master sends the initialize co mmand, which enables the next addressing commands for 15 minutes 2. the master sends the randomize command to make each ballast generate a 24-bit random number (stored fl ash in random_address) 3. the master searches the ballast with the lowest random number using search address and the compare command 4. the found ballast gets a unique (6-bit) short address (stored in flash), with command: program short adress 5. verify the programmed short address with verify short address command 6. this ballast is removed from the search process by withdraw command 7. this procedure is repeated unt il all ballasts have a short address. 8. the process is stopped by the terminate command physical selection addressing 1. the master sends command initialise 2. the master sends command physical selection 3. the master repeats command query sh ort address periodically until a ballast replies (this ballast is physically selected) 4. the master sends comm and program short address containing the ballast's address. 5. the master send s recall min level and recall max level using the short address for optical feedback for some seconds 6. steps 2 to 5 are repeated for all ballasts 1.5 data transfer register the data transfer register (dtr) is an 8-bit memory location of the ballast (in sram) to store temporary data from the master (using command data transfer register). after that, other commands are used to move the contents of the dtr to specific parameters (for example command store dtr as short address). 1.6 ballast operation some operational specifications for dali ballasts are: power on the dali commands (from master) are rece ived properly 0.5 sec after ?power-on?. earliest after another 100 ms the ballast will go to the predefined ?power-on level?
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 6 of 12 via preheat- and ignition phase (if applicable). duri ng the 100 ms interval the ballast shall react on a possible command if this ?power-on level? is not desired. logarithmic dimming curve the lowest dimming level of the ballast is 0.1 % and is coupled to the digital value ?1? in the range of 1 to 254 (absolute dimming). the highest arc power level of the ballast (100 %) is coupled to the digital value ?254?. a logarithmic dimming curve from 0.1 % to 100 % is defined (see fig 2 ). because of the many different influences, dim levels can only have the meaning of arc power level of a lamp. fig 2. example of a logarithmic dimming curve min and max control level programming a min level above or a max level below the actual power level will set the actual power level to the new min level or max level. programming a min level below or a max level above the actual power level will not affect the actual arc power level. a required level below the min level or above the max level will cause the ballast to operate at min level or max level. the arc power levels ?0? (off) and ?255? (mask) shall not be affected by the min and max level settings. 0 10 20 30 40 50 60 70 80 90 100 1 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254 8-bit control level "light level" (%)
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 7 of 12 fade time and fade rate some power control commands use the actual fade time (see table 1 ) constant to dim up/down to the required light level. the fade time constant can have a value from 0 to 15 that corresponds to a defined time in seconds (see table 2 ). some power control commands use the actual fade rate (see table 1 ) constant to dim up/down, during 200 milliseconds, to a new light level. the fade rate constant can have a value from 1 to 15 that w ill correspond to a def ined number of (level ) steps per second (see table 2 ). table 2. fade time and fade rate fade_time / fade_rate fade time (sec) fade rate (steps/sec) 0 0 not applicable 1 0.707 357.796 2 1.000 253.000 3 1.414 178.898 4 2.000 126.500 5 2.828 89.449 6 4.000 63.250 7 5.657 44.725 8 8.000 31.625 9 11.314 22.362 10 16.000 15.813 11 22.627 11.181 12 32.000 7.906 13 45.255 5.591 14 64.000 3.953 15 90.510 2.795 scene 1 to 16 ballasts can have 16 pre-defined light levels (s tored in flash/eeprom) called ?scenes? (see table 1 ). command go to scene is used to set the actual arc power level of the ballast to the value stored for scene 1 to 16 using the actual fade time. if the ballast does not belong to the scene, the arc power level rema ins unchanged. if the lamp is off it will be ignited with this command. 2. hardware the dali slave unit described in this application note is based on a low power and low cost lpc1112 microcontroller with an arm cortex m0 core (see fig 3 ). it uses timer ct32b1, match mat0 output, to generate a pwm signal, with a variable duty cycle, that represents t he lamp light level. the pwm signal is connected to the uba2014 ballast controller to perform the actual dimming of the lamp. the uba2014 hardware description is not part of this application note. for more information see application note an10181 (see references ).
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 8 of 12 to receive dali commands, general purpose timer ct32b0, capture cap0 input (p1.5) is used (capture and interrupt on both edges). the cap0 pin is also connected to gpio pin p2.6. this is needed to check high / low level (rising / falling edge) by software. to send dali slave backward frames again timer ct32b0 is used to control general purpose output pin (p2.0) as the dali send signal. 2.1 memory usage the lpc1112 has a total of 16 kb of on-chip flash divided into four sectors of 4 kb. code size used by the complete example application is ~6 kb (sector 0 and 1). sector 2 is not used (free for software expansion). sector 3 (starting at address 0x3000) is used to store the dali ballast variables (only 28 bytes used). these are updated using iap calls. 2.2 dali interface the dali hardware bus driver logic (including the optical isolation) is not handled in detail in this application note. 2.3 power supply in the example application the lpc1112 runs at a cclk of 2 mhz, derived from the on- chip irc of 12 mhz. if there?s no dali co mmunication active, the lpc1112 will enter ?sleep? mode. in this case the average current consumpti on is less than 1.3 ma (idd). this means a cheap bleeder resistor or a simple capacitive divider could be used to supply the lpc1112. fig 3. dali slave unit simplified block diagram pwm lpc1112 gpo cap gpi 4k7 1k dali 3v3 3v3 10k 8n2 82k uba2014
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 9 of 12 3. software 3.1 transmitting a dali message sending a frame is relatively easy, see dali_drv.c module. the implementation uses timer 0 interrupt every period ?te? to generate the dali message. sending a single bit via bi-phase encoding requires two interrupts, in order to produce a good transition. a '1' is sent by pulling down the line for one period, followed by releasing it for one period. sending a ?0? is exactly the opposite. a position counter is used to keep track of which bit is being transmitted. the counter runs at twic e the bit frequency (just like the interrupt), so bit 0 can be used to detect whether the first or the second period of this bit is to be transmitted. 3.2 decoding a dali message the best method to decode dali (manchester coding) messages is to detect the edges of the signal and measure the time between th ese edges. using a timer capture input of the lpc1112 this is easy to accomplish, because the input can capture and generate an interrupt at both rising and falling edge. at the falling edge the pulse ?high time? is captured and stored. at a rising edge the pulse ?low time? is captured, and the received bit(s) is decoded. there are no separate interrupts for rising and falling edge input capture, and it?s not possible to read the logi c level of the capture input pin. that?s why the capture input pin is also connected to a gpio input pin. 3.3 structure the dali slave unit software example is written in c language and compiled using keil?s uvision (arm7 realview, v4.12) free demo compiler. it performs the following main tasks: ? initialization: ? for lpc1112 microcontroller configurat ion the standard startup code (see startup_lpc11xx.s and system_lpc11xx.c ) from keil were used and set as cclk = irc / 6 = 2 mhz ? dali slave stack: ? dali driver: use timer 0 match 0 for s ending dali forward frames. use timer 0 capture 0 to receive dali backward frames (see dali_drv.c ) ? dali command: for decoding and exec ution of the received dali commands (see dali_cmd.c ) ? application (3 modules): ? main: handles ?sleep? mode, check and clear dali transmission event flags and take action (see main.c ) ? ballast: handles dimming, fading and translation of required lamp light level into actual pwm duty cycle. it uses the 10 ms systick timer and timer ct32b1 match mat0, to generate the pwm output signal (see ballast.c ). ? flash: handles the storage of the dali slave unit parameters, like min/max light levels, addresses and scene?s, usin g the on-chip flash of the lpc1112 (see flash.c ).
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 10 of 12 4. references for further details please refer to the following publications: ? datasheets / user manuals / application notes / example code: http://ics.nxp.com/microcontrollers/ ? an10181: ?36w tld application with the uba2014?: http://www.nxp.com/documents/user_manual/um10389.pdf ? an10760: ?dali master using the lpc2141? http://www.standardics.nxp.com/support/docum e nts/microcontrollers/zip/an10760.zip ? example programs: http://www.keil.com/download/
nxp semiconductors an10960 dali slave using the lpc1112 an10960 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 1 ? 22 july 2010 11 of 12 5. legal information 5.1 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 5.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such informatio n and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business inte rruption, costs related to the removal or replacement of any products or re work charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that cu stomer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and condi tions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product de scriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors produ cts are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is custom er?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as for the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is bas ed on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. evaluation products ? this product is provided on an ?as is? and ?with all faults? basis for evaluation purposes only. nxp semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non- infringement, merchantability and fitness for a particular purpose. the entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. in no event shall nxp semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inab ility to use the product, whether or not based on tort (including negligence), stri ct liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. notwithstanding any damages that cu stomer might incur for any reason whatsoever (including wit hout limitation, all damag es referenced above and all direct or general damages), the entire liability of nxp semiconductors, its affiliates and their suppliers and custom er?s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dolla rs (us$5.00). the foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 5.3 trademarks notice: all referenced brands, product names, service names and trademarks are property of their respective owners.
nxp semiconductors an10960 dali slave using the lpc1112 please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'legal information'. ? nxp b.v. 2010. all rights reserved. for more information, visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 22 july 2010 document identifier: an10960 6. contents 1. introduction ......................................................... 3 1.1 dali pr otoc ol ..................................................... 3 1.2 dali ba llast ....................................................... 4 1.3 frame stru cture.................................................. 4 1.4 addressing dali ballasts ................................... 5 1.5 data transfe r regi ster ....................................... 5 1.6 ballast oper ation ................................................ 5 2. hardwa re .............................................................. 7 2.1 memory usage ................................................... 8 2.2 dali inte rface .................................................... 8 2.3 power supply...................................................... 8 3. software ............................................................... 9 3.1 transmitting a da li message ............................ 9 3.2 decoding a da li me ssage................................. 9 3.3 structure............................................................. 9 4. references ......................................................... 10 5. legal information .............................................. 11 5.1 defini tions ........................................................ 11 5.2 disclai mers....................................................... 11 5.3 trademar ks ...................................................... 11 6. contents............................................................. 12

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